Research on Floorplanning for Heterogeneous and Partially Reconfigurable FPGAs

The development of integration technology has followed the famous Moores Law, which was stated by Gordon Moore in the year 1965, that “the number of transistors per chip would grow exponentially (double every 18 months)”. In fact, the doubling period has even shortened to a mere 12 months. Field programmable gate arrays (FPGAs) have been popular for more than 20 years, and the market size has been increased to about 2.75 billion dollar in 2010. FPGAs are digital integrated circuits (ICs) that contain programmable blocks of logic along with configurable interconnects between these blocks. The functionality of FPGAs can be customized in the field like programmable logic devices (PLDs), meanwhile, the millions of gates included by current FPGAs can implement extremely large and complex functions like application specific integrate circuits (ASICs). FPGAs are characterized by heterogeneity of resources and partial reconfigurability. Embedded blocks such as digital signal processors (DSPs), embedded microprocessor cores, high speed IOs, clock synchronization circuitry, system on chip (SoC) components have been added to modern high performance FPGAs. The use of these embedded blocks can improve the density and performance of FPGAs. Therefore, more and more components will be added to FPGAs in the near future, which means the resource utilization problem is going to be very important in order to reduce the cost and area of the FPGA chips. Reconfigurable computing as a concept which was introduced by Estrin at 1963 can fill the gap between hardware and software, it is reconfigurable while much